1. Field of the Invention
The present invention relates a multiplier and more particularly, to a multiplier for two analog signals using quadritail circuits formed of bipolar transistors or Metal-Oxide-Semiconductor (MOS) transistors, which is realized on semiconductor integrated circuits.
2. Description of the Prior Art
An analog multiplier constitutes a functional circuit block essential for analog signal applications. Recently, semiconductor integrated circuits have been made finer and finer and as a result, their power source voltages have been decreasing from 5 V to 3.3 or 3 V. Under such a circumstance, low-voltage circuits which can be operated at such a low voltage as 3 V has been required to be developed. In the case, the linear ranges of the input voltages of the multipliers need to be wide as much as possible.
A Gilbert multiplier cell is well known as a bipolar multiplier. However, the Gilbert multiplier cell has such a structure that bipolar transistor-pairs are provided in a two-stage stacked manner and as a result, it cannot respond to reduction of the operating power source voltage.
Besides, the Complementary MOS (CMOS) technology has become recognized to be the optimum process technology for Large Scale Integration (LSI), so that multipliers which can be realized using the CMOS technology have been required.
The inventor developed multipliers as shown in FIGS. 1, 4 and 7 and filed Japanese patent applications about them. With these multipliers, two squaring circuits are arranged in a line transversely, not in a stack manner, to be driven by the same power source voltage. The circuit configuration was developed such that the product of first and second input voltages is given by subtracting the square of the difference of the first and second input voltages from the square of the sum thereof.
The above multipliers developed by the inventor were named "quarter-square multipliers" since the constant "4" of involution contained in the term of the product was changed to "1".
First, the multiplier shown in FIG. 1 is disclosed in the Japanese Non-Examined Patent Publication No. 5-94552 (Japanese Patent Application No. 4-72629). In FIG. 1, the multiplier includes a first squaring circuit made of bipolar transistors Q1', Q2', Q3' and Q4' and a second squaring circuit made of bipolar transistors Q5', Q6', Q7' and Q8'.
In the first squaring circuit, the transistors Q1' and Q2' form a first unbalanced differential pair driven by a first constant current source (current: I.sub.0) and the transistors Q3' and Q4' form a second unbalanced differential pair driven by a second constant current source (current: I.sub.0). The transistor Q1' is K times in emitter size or area as much as the transistor Q2' and the transistor Q4' is K times in emitter size as much as the transistor Q3'.
Emitters of the transistors Q1' and Q2' are connected in common to the first constant current source, and emitters of the transistors Q3' and Q4' are connected in common to the second constant current source.
In the second squaring circuit, the transistors Q5' and Q6' form a third unbalanced differential pair driven by a third constant current source (current: I.sub.0) and the transistors Q7' and Q8' form a fourth unbalanced differential pair driven by a fourth constant current source (current: I.sub.0). The transistor Q5' is K times in emitter size as much as the transistor Q6' and the transistor Q8' is K times in emitter size as much as the transistor Q7'.
Emitters of the transistors Q5' and Q6' are connected in common to the third constant current source, and emitters of the transistors Q7' and Q8' are connected in common to the fourth constant current source.
Bases of the transistors Q1' and Q3' are coupled together to be applied with a first input voltage V.sub.x, and bases of the transistors Q2' and Q4' are coupled together to be applied with a second input voltage V.sub.y.
Bases of the transistors Q5' and Q7' are coupled together to be applied with the first input voltage V.sub.x, and bases of the transistors Q6' and Q8' are coupled together to be applied in opposite phase with the second input voltage V.sub.y, or -V.sub.y.
The transfer characteristics and the transconductance characteristics of the multiplier are shown in FIGS. 2 and 3, respectively, where K is e.sup.2 (.apprxeq.7.389). A differential output current .DELTA.I shown in FIG. 2 is defined as the difference of output currents I.sub.p and I.sub.q shown in FIG. 1, or (I.sub.p -I.sub.q).
FIG. 2 shows the relationship between the differential output current .DELTA.I and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 3 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter.
Second, the prior-art multiplier developed by the inventor shown in FIG. 4 is disclosed in the Japanese Non-Examined Patent Publication No. 4-34673 (1992). In FIG. 4, the multiplier includes a first squaring circuit made of MOS transistors M1', M2', M3' and M4' and a second squaring circuit made of MOS transistors M5', M6', M7' and M8'.
In the first squaring circuit, the transistors M1' and M2' form a first unbalanced differential pair driven by a first constant current source (current: I.sub.0), and the transistors M3' and M4' form a second unbalanced differential pair driven by a second constant current source (current: I.sub.0). The transistor M2' is K times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M1', and the transistor M3' is K times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M4'.
Sources of the transistors M1' and M2' are connected in common to the first constant current source, and sources of the transistors M3' and M4' are connected in common to the second constant current source.
In the second squaring circuit, the transistors M5' and M6' form a third unbalanced differential pair driven by a third constant current source (current: I.sub.0), and the transistors M7' and M8' form a fourth unbalanced differential pair driven by a fourth constant current source (current: I.sub.0). The transistor M6' is K times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M5', and the transistor M7' is K times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M8'.
Sources of the transistors M5' and M6' are connected in common to the third constant current source, and sources of the transistors M7' and M8' are connected in common to the fourth constant current source.
Gates of the transistors M1' and M3' are coupled together to be applied with a first input voltage V.sub.x, and gates of the transistors M2' and M4' are coupled together to be applied in opposite phase with a second input voltage V.sub.y, or -V.sub.y.
Gates of the transistors M5' and M7' are coupled together to be applied with the first input voltage V.sub.x, and gates of the transistors M6' and M8' are coupled together to be applied with the second input voltage V.sub.y.
In FIG. 4, the transconductance parameters of the transistors M1', M4', M5' and M8' are equal to be .beta., and those of the transistors M2', M3', M6' and M7' are equal to be K.beta..
The transfer characteristics and the transconductance characteristics of the multiplier are shown in FIGS. 5 and 6, respectively, where K is 5. A differential output current .DELTA.I shown in FIG. 5 is defined as the difference of output currents I.sup.+ and I.sup.- shown in FIG. 4, or (I.sup.+ -I.sup.-).
FIG. 5 shows the relationship between the differential output current .DELTA.I and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 6 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter.
Third, the prior-art multiplier developed by the inventor shown in FIG. 7 is disclosed in IEICE TRANSACTIONS ON FUNDAMENTALS, Vol. E75-A, No. 12, December, 1992. In FIG. 7, the multiplier includes a first squaring circuit made of MOS transistors M1", M2", M3" and M4" and a first constant current source (current: I.sub.0) for driving the transistors M1", M2", M3" and M4", and a second squaring circuit made of MOS transistors M5", M6", M7" and M8" and a second constant current source (current: I.sub.0) for driving the transistors M5", M6", M7" and M8". The transistors M1", M2", M3", M4", M5", M6", M7" and M8" are equal in capacity or ratio (W/L) of a gate-width W to a gate-length L to each other.
The first and second squaring circuits are named as "quadritail circuits" or "quadritail cells", respectively.
In the first quadritail circuit, sources of the transistors M1", M2", M3" and M4" are connected in common to the first constant current source. Drains of the transistors M1" and M2" are coupled together and drains of the transistors M3" and M4" are coupled together. A gate of the transistor M1" is applied with a first input voltage V.sub.x, and a gate of the transistor M2" is applied in opposite phase with a second input voltage V.sub.y, or -V.sub.y. Gates of the transistor M3" and M4" are coupled together to be applied with a middle point voltage of the voltage applied between the gates of the transistors M1" and M2", or (1/2)(V.sub.x +V.sub.y), which is obtained through resistors (resistance: R).
Similarly, in the second quadritail circuit, sources of the transistors M5", M6", M7" and M8" are connected in common to the second constant current source. Drains of the transistors M5" and M6" are coupled together and drains of the transistors M7" and M8" are coupled together. A gate of the transistor M5" is applied with the first input voltage V.sub.x, and a gate of the transistor M6" is applied with the second input voltage V.sub.y. Gates of the transistor M7" and M8" are coupled together to be applied with a middle point voltage of the voltage applied between the gates of the transistors M5" and M6", or (1/2)(V.sub.x -V.sub.y), which is obtained through resistors (resistance: R).
Between the first and second quadritail circuits, the drains coupled together of the transistors M1" and M2" and the drains coupled together of the transistors M7" and M8" are further coupled together to form one of differential output ends of the multiplier. The drains coupled together of the transistors M3" and M4" and the drains coupled together of the transistors M5" and M6" are further coupled together to form the other of the differential output ends thereof.
The transfer characteristics and the transconductance characteristics of the multiplier are shown in FIGS. 8 and 9, respectively. A differential output current .DELTA.I shown in FIG. 8 is defined as the difference of output currents I.sub.p and I.sub.Q shown in FIG. 7, or (I.sub.P -I.sub.Q).
FIG. 8 shows the relationship between the differential output current .DELTA.I and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 9 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter.
Fourth, the prior-art multiplier shown in FIG. 10 was developed by Wang, which is disclosed in IEEE Journal of Solid-State Circuits, Vol. 26, No. 9, September, 1991. The circuit in FIG. 10 is modified by the inventor to clarify its characteristics.
In FIG. 10, the multiplier includes one quadritail circuit made of MOS transistors M1'", M2'", M3'" and M4'" and a constant current source (current: I.sub.0) for driving the transistors M1'", M2'", M3'" and M4'". The transistors M1'", M2'", M3'" and M4'" are equal in capacity (W/L) to each other.
Sources of the transistors M1'", M2'", M3'" and M4'" are connected in common to the constant current source. Drains of the transistors M1'" and M4'" are coupled together to form one of differential output ends on the multiplier, and drains of the transistors M2'" and M3'" are coupled together to form the other of the differential output ends thereof.
A gate of the transistor M1'" is applied with a first input voltage (1/2)V.sub.x based on a reference point, and a gate of the transistor M2'" is applied in opposite phase with the first input voltage (1/2)V.sub.x or -(1/2)V.sub.x based on the reference point. A gate of the transistor M3'" is applied with a voltage of the half difference of the first input voltage and a second input voltage, or (1/2)(V.sub.x -V.sub.y). A gate of the transistor M4'" is applied with the voltage (1/2)(V.sub.x -V.sub.y) in opposite phase, or (-1/2)(V.sub.x -V.sub.y).
The transfer characteristics and the transconductance characteristics of the multiplier, which were obtained through analysis by the inventor, are shown in FIGS. 11 and 12, respectively. A differential output current .DELTA.I shown in FIG. 11 is defined as the difference of output currents I.sub.L and I.sub.R shown in FIG. 10, or (I.sub.L -I.sub.R).
FIG. 11 shows the relationship between the differential output current .DELTA.I and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 12 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter.
The multiplier formed of bipolar transistors shown in FIG. 1 has input voltage ranges of superior linearity which is substantially equal to those of the Gilbert multiplier cell. The prior-art multipliers shown in FIGS. 4, 7 and 10, each of which is MOS transistors, have input voltage ranges of superior linearity comparatively wider than those of the Gilbert multiplier cell, respectively. However, when operating at a low power source voltage such as 3 or 3.3 V, input voltage ranges of superior linearity cannot be expanded in all of the prior-art multipliers.